It has been known that corner conduction in trench isolated n-MOSFETs may be a significant contributor to standby current in low standby power ULSI applications, as described in A. Bryant, et al "The current-carrying corner inherent to trench isolation", IEEE Electron Device Letters, vol 14, no. 8, pp. 412-414, 1993 and B. Davari, et al "A variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS" 1988 IEDM Technical Digest, pp. 92-95, 1988. A manifestation of corner conduction is inverse narrow channel effect when the standard current definition of V.sub.t (I.sub.vt =40.times. (W.sub.des /L.sub.des)nA) is applied. However, corner conduction in buried-channel p-MOSFETs has not, heretofore, been recognized as a concern. In buried-channel p-MOSFETs, the polarity of the work function difference between the N+ poly gate and the buried p-layer depletes the buried layer of carriers at low gate voltages. Due to the geometrically enhanced field at the silicon corner, it is expected that, when the doping is uniform across the device width, the magnitude of V.sub.t (the threshold voltage) at the corners of these devices is greater than at mid-channel. This leads to a normal narrow channel effect.